VLSI architectures for turbo codes
Maurizio Zamboni | Politecnico di Torino
Synthesis of low-leakage PD-SOI circuits with body-biasing | Proceedings of the 2001 international symposium on Low power electronics and design
Resta da stabilire dove iniziare il testo (paragrafo, font, corpo, ecc
MEDEA: A Hybrid Shared-memory/Message-passing Multiprocessor NoC-based Architecture
POLITECNICO DI TORINO Repository ISTITUZIONALE
Laboratorio#1 del corso di Elettronica dei Sistemi Digitali al PoliTo | Guide, Progetti e Ricerche di Elettronica Dei Sistemi Digitali | Docsity
An Electromigration and Thermal Model of Power Wires for a Priori High-Level Reliability Prediction
Maurizio Zamboni - Google Scholar
Design of a force sensor for an haptic and touch interface - Webthesis
PDF) Novel JPEG 2000 Compliant DWT and IWT VLSI Implementations | M. Zamboni - Academia.edu
People – ToPoliNano
A Lowv-ower CMOS 2-PPM Demodulator for Energy Detection IR4JWB Receivers
10 "Maurizio Zamboni" profiles | LinkedIn
A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory Errors
Algorithms Parallelization in ASIC Design - Webthesis
Maurizio Zamboni – ToPoliNano
Maurizio MARTINA | Politecnico di Torino, Turin | polito | DET - Department of Electronics and Telecommunications | Research profile
Final Presentation of the course “Workshop: Innovative Systems” 2020/2021 – Politecnico di Torino IEEE Student Branch
A Standard Cell Approach for MagnetoElastic NML Circuits
Design of a Reconfigurable In-Memory Neural Network Accelerator - Webthesis
PDF) FPGA Fully Reconfigurable Lifting Kernel for Multimedia Processing | M. Zamboni - Academia.edu
People – ToPoliNano
Comunicati stampa – PoliToBlog
